Typically, a digital imager array includes a focal plane array of pixel cells, each one of the cells including a photoconversion device, e.g. a photogate, photoconductor, or a photodiode. In one such imager, known as a CMOS imager, a readout circuit is connected to each pixel cell which typically includes a source follower output transistor. The photoconversion device converts photons to electrons which are typically transferred to a charge storage region, which may be a floating diffusion region, connected to the gate of the source follower output transistor. A charge transfer device (e.g., transistor) can be included for transferring charge from the photoconversion device to the floating diffusion region. In addition, such imager cells typically have a transistor for resetting the floating diffusion region to a predetermined charge level prior to charge transference. The output of the source follower transistor is gated as an output signal by a row select transistor.
Exemplary CMOS imaging circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an imaging circuit are described, for example, in U.S. Pat. No. 6,140,630 to Rhodes, U.S. Pat. No. 6,376,868 to Rhodes, U.S. Pat. No. 6,310,366 to Rhodes et al., U.S. Pat. No. 6,326,652 to Rhodes, U.S. Pat. No. 6,204,524 to Rhodes, and U.S. Pat. No. 6,333,205 to Rhodes. The disclosures of each of the forgoing are hereby incorporated by reference herein in their entirety.
FIG. 1 illustrates a block diagram of an exemplary imager device 308 having a pixel array 200 with each pixel cell being constructed as described above. Pixel array 200 comprises a plurality of pixels arranged in a predetermined number of columns and rows. The pixels of each row in array 200 are all turned on at the same time by a row select line, and the pixels of each column are selectively output by respective column select lines. A plurality of row and column lines are provided for the entire array 200. The row lines are selectively activated by a row driver 210 in response to row address decoder 220. The column select lines are selectively activated by a column driver 260 in response to column address decoder 270. Thus, a row and column address is provided for each pixel. The CMOS imager is operated by the timing and control circuit 250, which controls address decoders 220, 270 for selecting the appropriate row and column lines for pixel readout. The control circuit 250 also controls the row and column driver circuitry 210, 260 such that these apply driving voltages to the drive transistors of the selected row and column lines. The pixel column signals, which typically include a pixel reset signal (Vrst) and a pixel image signal (Vsig) for selected pixels, are read by a sample and hold circuit 261 associated with the column device 260. A differential signal (Vrst−Vsig) is produced by differential amplifier 262 for each pixel which is digitized by analog to digital converter 275 (ADC). The analog to digital converter 275 supplies the digitized pixel signals to an image processor 280 which forms a digital image.
Pixels of conventional image sensors, such as a CMOS imager, employ a photoconversion device as shown in FIG. 2. This photoconversion device may typically include a photodiode 59 having a p-region 21 and n-region 23 in a p-substrate. The pixel also includes a transfer transistor with associated gate 25, a floating diffusion region 16, and a reset transistor with associated gate 29. Photons striking the surface of the photodiode 59 generate electrons which are collected in region 23. When the transfer gate is on, the photon-generated electrons in region 23 are transferred to the floating diffusion region 16 as a result of the potential difference existing between the photodiode 59 and floating diffusion region 16. The charges are converted to voltage signals by a source follower transistor (not shown). Prior to charge transfer, the floating diffusion region 16 is set to a predetermined low charge state by turning on the reset transistor having gate 29 which causes electrons in region 16 to flow into a voltage source connected to a source/drain 17. Regions 55 are STI insulation regions for isolating the pixels from one another.
FIG. 3 is a potential diagram for the image sensor shown in FIG. 2. The full well charge capacity of the photodiode 59 is in the shaded area under heading “PD” and is a function of a pinned potential (VPIN) and photodiode capacitance (CPD). When the number of electrons generated reaches the charge capacity, the photodiode is saturated and cannot respond to any further photons. Generated electrons collected in region 23 are transferred from the photodiode 59 to the floating diffusion region 16. The floating diffusion region charge storage capacity also has a saturation voltage, shown as the shaded region under the heading “FD.” The bottom potential VRST represents a reset voltage of the floating diffusion region 16. When the transfer gate 25 is on, the barrier potential separating the photodiode 59 and floating diffusion region 16 is lowered, as represented by the dotted line in FIG. 3. As a result, electrons move from the photodiode 59 to the floating diffusion region 16.
As shown in the graph of FIG. 4, the output voltage response based on the charge transferred to region 16 is a linear function of the light intensity up to the point where the response reaches the region 16 saturation point (VSAT). The region 16 saturation point limits the dynamic range of the pixel and the ability of the image sensor to capture intra-scene intensity variations under certain light conditions.